Usage driven relevance analysis for IP cores

Understanding an unknown hardware design is inherently hard. We propose usage-driven relevance analysis as a technique for design understanding. Our approach gathers data about an unknown design through Information Flow Tracking (IFT), a technique known from security analysis. IFT data from existing testbenches that represent typical design usage is automatically aggregated to compactly present relevant and interesting parts of a hardware design. We propose a set of aggregation metrics to guide a designer when debugging, optimizing, and understanding hardware designs. Our evaluation demonstrates how usage-driven relevance analysis effectively supports designers by examining two use cases on how our approach provides information about the most and least used parts in a design and about how long specific information, e.g., a fault, stays in the design before reaching an output.

Subjects

design understanding | hardware | information flow tracking | Verilog

DDC Class

600: Technology

Options

Usage driven relevance analysis for IP cores