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  4. A Variable Node Design with Check Node Aware Quantization Leveraging 2-Bit LDPC Decoding
 
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A Variable Node Design with Check Node Aware Quantization Leveraging 2-Bit LDPC Decoding

Citation Link: https://doi.org/10.15480/882.13979
Publikationstyp
Conference Paper
Date Issued
2022-12
Sprache
English
Author(s)
Mohr, Philipp  orcid-logo
Bauch, Gerhard  
Institut
Nachrichtentechnik E-8  
TORE-DOI
10.15480/882.13979
TORE-URI
http://hdl.handle.net/11420/14584
Start Page
3484
End Page
3489
Citation
IEEE Global Communications Conference (GLOBECOM 2022) 3484-3489
Contribution to Conference
IEEE Global Communications Conference, GLOBECOM 2022  
Publisher DOI
10.48550/arXiv.2211.06973
10.1109/GLOBECOM48099.2022.10000665
Scopus ID
2-s2.0-85146952561
ArXiv ID
2211.06973v1
For improving coarsely quantized decoding of LDPC codes, we propose a check node aware design of the variable node update. In contrast to previous works, we optimize the variable node to explicitly maximize the mutual information preserved in the check-to-variable instead of the variable-to-check node messages. The extended optimization leads to a significantly different solution for the compression operation at the variable node. Simulation results for regular LDPC codes confirm that the check node aware design, especially for very coarse quantization with 2- or 3-bit messages, achieves performance gains of up to 0.2 dB - without additional hardware costs. We also show that the 2-bit message resolution enables a very efficient implementation of the check node update, which requires only 2/9 of the 3-bit check node's transistor count and reduces the signal propagation delay by a factor of 4.
Subjects
Computer Science - Information Theory
Mathematics - Information Theory
DDC Class
004: Computer Sciences
510: Mathematics
Lizenz
https://creativecommons.org/licenses/by/4.0/
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