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  4. An IEEE 754-2008 decimal parallel and pipelined FPGA floating-point multiplier
 
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An IEEE 754-2008 decimal parallel and pipelined FPGA floating-point multiplier

Publikationstyp
Conference Paper
Date Issued
2010-12-01
Sprache
English
Author(s)
Baesler, Malte  
Voigt, Sven-Ole  
Teufel, Thomas  
Institut
Zuverlässiges Rechnen E-19  
TORE-URI
http://hdl.handle.net/11420/8531
Start Page
489
End Page
495
Article Number
5694299
Citation
Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010: 5694299, 489-495 (2010-12-01)
Contribution to Conference
20th International Conference on Field Programmable Logic and Applications, FPL 2010  
Publisher DOI
10.1109/FPL.2010.98
Scopus ID
2-s2.0-79951754666
Publisher
EEE
Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, scientific, commercial, and financial applications. In this paper we present an IEEE 754-2008 compliant parallel decimal floating-point multiplier designed to exploit the features of Virtex-5 FPGAs. It is an extension to a previously published decimal fixed-point multiplier. The decimal floating-point multiplier implements early estimation of the shift-left amount and efficient decimal rounding. Additionally, it provides all required rounding modes, exception handling, overflow, and gradual underflow. Several pipeline stages can be added to increase throughput. Furthermore, different modifications are analyzed including shifting by means of hard-wired multipliers and delayed carry propagation adders.
DDC Class
004: Informatik
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