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Single poly PMOS-based CMOS-compatible low voltage OTP
Publikationstyp
Conference Paper
Date Issued
2005
Sprache
English
Author(s)
First published in
Number in series
5837
Start Page
953
End Page
960
Article Number
110
Citation
Proceedings of SPIE - The International Society for Optical Engineering Volume 5837 pt. II, pp. 953 - 960, art. no. 110 (2005)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
SPIE
A PMOS-based non-volatile memory cell fully compatible with standard CMOS fabrication processes is presented. It consists of a PMOS access transistor in series with a PMOS transistor whose gate is left floating. The cell configuration eliminates the requirement of a control gate, and therefore can be fabricated without using double poly gates. The cell saves area compared to other single poly non-volatile memory cells based on CMOS approaches, which require both NMOS and PMOS transistors. It also avoids the risk of latch-up. The cells were fabricated using a 350nm standard CMOS process. The programming mechanism of the cell is hot electron injection. The programming operation can be performed at programming voltages as low as |Vds|=4.5V. The cell can be used as a low voltage OTP and provides a very cheap alternative to integrate OTPs in CMOS ICs without any modification of the fabrication process.
Subjects
CMOS compatible
Low voltage
OTP
Single-poly
DDC Class
621.3: Electrical Engineering, Electronic Engineering