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Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms
Publikationstyp
Conference Paper
Date Issued
2007-11-12
Sprache
English
Author(s)
Institut
TORE-URI
Start Page
633
End Page
637
Article Number
4380734
Citation
Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL: 4380734, 633-637 (2007-12-01)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE Operations Center
In this paper we present an FPGA-based dataflow architecture that both efficiently computes parallel algorithms using dedicated FPGA resources and scales well to multi-FPGA chip designs while the overall communication bandwidth increases. The basic idea is based on reconfiguration. In contrast to the concept of partially reconfiguring FPGAs, our approach is to connect computational units via a dynamically variable topology. The latter consists of dedicated switches which are individually controlled by simple shift registers. Hence, the computational result is a function of the currently configured interconnection pattern that can be updated within one single clock cycle. The scalability of this architecture is shown on a high-performance parallel FFT.
DDC Class
004: Informatik
510: Mathematik