Design of a MCML gate library applying multiobjective optimization

Start Page
81
End Page
85
Article Number
4208898
Citation
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), Porto Alegre, Brazil, 2007, pp. 81-85
Contribution to Conference
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2007  
Publisher DOI
10.1109/ISVLSI.2007.38
Scopus ID
2-s2.0-36348969303
Publisher
IEEE Computer Society
ISBN
978-0-7695-2896-0
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multiobjective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 μm technology are presented.
Subjects
Design space exploration
Genetic algorithms
MOS current mode logic (MCML)
Multi-objective optimization
Pareto front
DDC Class
621.3: Electrical Engineering, Electronic Engineering