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A scalable 64 channel neurostimulator based on a hybrid architecture of current steering DAC
Publikationstyp
Conference Paper
Date Issued
2014
Sprache
English
Author(s)
Meza Cuevas, Mario Alberto
Schröder, Dietmar
Start Page
111
End Page
114
Article Number
6783218
Citation
Middle East Conference on Biomedical Engineering (MECBME), 2014, Doha, Qatar, 17-20 Feb. 2014
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE
ISBN
978-1-4799-4798-0
978-1-4799-4799-7
In this work a 130 nm CMOS 64 channel neural stimulator is presented, which is scalable by connecting it in a daisy chain configuration, for applications requiring larger number of stimulation sites, as it is of interest for retinal implants with improved resolution. Each channel is composed of a hybrid architecture current steering 8 bit DAC, enabling the low power consumption and high channel integration on a small chip area. Besides, the DAC allows stimulating with several waveforms in order to save stimulation energy. An on-chip module was implemented to control galvanostatic deposition of PEDOT on the electrodes. A schema is presented to avoid the residual charge due to cross electrode stimulation and process mismatch. © 2014 IEEE.
DDC Class
621.3: Electrical Engineering, Electronic Engineering