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# Mathematical abstraction in a simple programming tool for parallel embedded systems

Publikationstyp

Book part

Publikationsdatum

2019

Sprache

English

Author

Institut

TORE-URI

First published in

Number in series

11657 LNCS

Start Page

32

End Page

50

Citation

Lecture Notes in Computer Science (11657 LNCS): 32-50 (2019)

Contribution to Conference

Publisher DOI

Scopus ID

Publisher

Springer

We explain the application of a mathematical abstraction to arrive at a simple tool for a variety of parallel embedded systems. The intended target systems are networks of processors used in numeric applications such as digital signal processing and robotics. The processors can include mixes of simple processors configured on an FPGA (field programmable gate array) operating on various number codes. To cope with such hardware and to be able to implement numeric computations with some ease, a new language, π-Nets, was needed and supported by a compiler. Compilation builds on a netlist identifying the processors available for the particular application. It also integrates facilities to simulate entire many-threaded applications to analyze for the precision and the specified timing. The main focus of the paper will be on the language design, however, that firmly builds on mathematical considerations. The abstraction chosen to deal with the various codes is to program on the basis of real numbers, and to do so in terms of predefined operations on tuples. A separate step is then needed to execute on some processor. To deal with errors, the number set is enlarged to also contain ‘invalid’ data. Further simplification is through the generous overloading of scalar operations to tuples e.g. used as complex signal vectors. Operating on the reals also fits to high-precision embedded computing or performing computations on one or several PCs. To these features, π-Nets adds simple, non standard structures to handle parallelism and real time control. Finally, there is a simple way to specify the target networks with enough detail to allow for compilation and even modeling configurable, FPGA based components in an original way. The paper concludes by a short presentation of an advanced target and by a funny example program.