Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction

Citation
IEEE Nordic Circuits and Systems Conference, NORCAS 2024
Contribution to Conference
IEEE Nordic Circuits and Systems Conference, NORCAS 2024
Publisher DOI
10.1109/NorCAS64408.2024.10752448
Scopus ID
2-s2.0-85211901787
ISBN
[9798331517663]
Efficient compression of Ballistocardiography (BCG) data is critical for wearable and Ultra-Low-Power (ULP) applications, particularly in space-bound missions. This paper presents a hardware accelerator for data compression integrated into a NEORV32 RISC-V system specifically designed to enhance the performance of BCG sensors in resource-constraint environments. Utilizing hardware-accelerated Modified-Delta encoding with a software-based simple bit-packing compression can significantly improve real-time data transmission and storage efficiency. Implemented on the Lattice iCE40UP5K FPGA, the proposed method can achieve up to 13× speed improvement over traditional software solutions while maintaining a minimal footprint of 3719 Look-Up Tables (LUTs). This technique paves the way for ultra-efficient, wearable BCG sensors, which are crucial for, e.g. deep-space missions where energy and storage are at a premium.
Subjects
BCG | Data compression | FPGA | RISC-V | SCG