Timing-aware analysis of shared cache interference for non-preemptive scheduling

In multi-core architectures, the last-level cache (LLC) is often shared between cores. Sharing the LLC leads to inter-core interference, which impacts system performance and predictability. This means that tasks running in parallel on different cores may experience additional LLC misses as they compete for cache space. To compute a task’s worst-case execution time (WCET), a safe bound on the inter-core cache interference has to be determined. We propose an interference analysis for set-associative shared least-recently-used caches. The analysis leverages timing information to establish tight bounds on the worst-case interference and classifies individual accesses as either cache hits or potential cache misses. We evaluated the analysis performance for systems containing 2 and 4 cores using shared caches up to 64 KB. The evaluation shows an average WCET reduction of up to 23.3% for dual-core systems and 8.5% for quad-core systems.

Subjects

Event-arrival curve | Multi-core | Shared cache | WCET analysis

DDC Class

004: Computer Sciences

621.3: Electrical Engineering, Electronic Engineering

Funding(s)

Projekt DEAL

Publication version

publishedVersion

Lizenz

https://creativecommons.org/licenses/by/4.0/

Name

s11241-024-09430-8.pdf

Type

Main Article

Size

2.29 MB

Format

Adobe PDF

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Timing-aware analysis of shared cache interference for non-preemptive scheduling