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  4. Robust LFSR-based scrambling to mitigate stencil attack on main memory
 
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Robust LFSR-based scrambling to mitigate stencil attack on main memory

Citation Link: https://doi.org/10.15480/882.16050
Publikationstyp
Journal Article
Date Issued
2025-09-26
Sprache
English
Author(s)
Kumar, Gaurav
Nanote Kushal Pravin  
Prasad, Yamuna  
Lal, Sohan  
Massively Parallel Systems E-EXK5  
Ahlawat, Satyadev  
TORE-DOI
10.15480/882.16050
TORE-URI
https://hdl.handle.net/11420/58290
Journal
ACM transactions on embedded computing systems  
Volume
24
Issue
5 s
Article Number
102
Citation
ACM Transactions on Embedded Computing Systems 24 (5s): 102: (2025)
Publisher DOI
10.1145/3758321
Scopus ID
2-s2.0-105018576589
Publisher
ACM Press
Main memory plays a pivotal role in the storage of computational data in a wide range of applications, including highly sensitive assets such as banking transactions, cryptographic keys, and user credentials. However, memory systems remain vulnerable to advanced physical and side-channel attacks, including cold boot attacks that exploit residual data after power-down. To mitigate such risks, Intel’s DDR3 memory scrambler uses a Linear Feedback Shift Register (LFSR)-based stream cipher to obscure memory contents. Nevertheless, this mechanism has been shown to be susceptible to stencil attack, a cold boot technique that reconstructs the scrambling key by leveraging the linear and periodic nature of the keystream. This article proposes a novel, lightweight, and secure scrambling architecture based on a generic LFSR designed to enhance the security of DDR3 memory against cold boot attacks. The proposed generic LFSR-based mechanism eliminates differential keystream periodicity by introducing an address- and seed-dependent LFSR structure, thereby rendering differential key recovery techniques computationally infeasible. Furthermore, unlike traditional AES-based memory encryption that incurs high latency and area overhead, the proposed approach achieves comparable security guarantees with low hardware complexity and zero access latency. The hardware implementation results on the Xilinx VCU118 FPGA show that the proposed scheme consumes only 252 LUTs, 256 registers and 104 slices, comparable to the Intel DDR3 scrambler, while offering superior resilience against the cold boot, warm boot, and probing attacks. These results demonstrate the practicality of the proposed scheme for secure memory systems in resource-constrained environments.
Subjects
DRAM security
LFSR
memory disclosure attacks
memory scrambling
stencil attack
DDC Class
004: Computer Sciences
005: Computer Programming, Programs, Data and Security
621: Applied Physics
Publication version
publishedVersion
Lizenz
https://creativecommons.org/licenses/by-nc/4.0/
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