Resource-Aware Optimization of FPGA OpenCL Kernels

Although the OpenCL platform guarantees the portability of the written kernels among heterogeneous devices, performance on the other hand is far from comparable between them. Differences in performance between devices like the CPU, GPU and FPGA are related to the nature of the computation models and the underlying hardware architecture that has already been established, specially For FPGA migrated kernels, where performance is left to the user to optimize for the desired requirements, which requires both time and experience. This study introduces an automated optimization strategy of OpenCL kernel targeting the FPGA. The strategy aware of the resource constrained environment, focuses on the loop pipelining, loop unrolling and array partitioning in a cooperative manner, to produce an efficient kernel implementation. experimental results shows that speed ups could reach up to 126.96x the original performance within less than 400 ms of time cost for the developed tool.

Subjects

FPGA

HLS

OpenCL

Optimizing

Resources

Options

Resource-Aware Optimization of FPGA OpenCL Kernels