Noise efficient integrated amplifier designs for biomedical applications

The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise floor is 9.9 nV/√ Hz with a 10 µA bias current, which results in a NEF of 1.2.

Subjects

Chopper stabilized

CMOS

Current reuse

Folded-cascode

Inverter based

Lateral BJT

Low noise

Low power

Multistage

NEF

Noise efficiency

OTA

DDC Class

600: Technik

More Funding Information

This work was funded by the German Research Foundation (Deutsche Forschungsgemeinschaft, DFG) through the collaborative Research Centre CRC 1261 “Magnetoelectric Sensors: From Composite Materials to Biomagnetic Diagnostics” via the project A4.

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publishedVersion

Lizenz

https://creativecommons.org/licenses/by/4.0/

Name

electronics-10-01522-v2.pdf

Size

3.74 MB

Format

Adobe PDF

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Noise efficient integrated amplifier designs for biomedical applications