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A Constant Time Full Hardware Implementation of Streamlined NTRU Prime
Publikationstyp
Conference Paper
Date Issued
2020-11
Sprache
English
Author(s)
First published in
Number in series
12609 LNCS
Start Page
3
End Page
17
Citation
International Conference on Smart Card Research and Advanced Applications (CARDIS 2020)
Contribution to Conference
Publisher DOI
Scopus ID
This paper presents a constant time hardware implementation of the NIST round 2 post-quantum cryptographic algorithm Streamlined NTRU Prime. We implement the entire KEM algorithm, including all steps for key generation, encapsulation and decapsulation, and all en- and decoding. We focus on optimizing the resources used, as well as applying optimization and parallelism available due to the hardware design. We show the core en- and decapsulation requires only a fraction of the total FPGA fabric resource cost, which is dominated by that of the hash function, and the en- and decoding algorithm. For the NIST Security Level 3, our implementation uses a total of 1841 slices on a Xilinx Zynq Ultrascale+ FPGA, together with 14 BRAMs and 19 DSPs. The maximum achieved frequency is 271 MHz, at which the key generation, encapsulation and decapsulation take 4808 μ s, 524 μ s and 958 μ s respectively. To our knowledge, this work is the first full hardware implementation where the entire algorithm is implemented.
Subjects
FPGA
Hardware
Key encapsulation mechanism
Lattice-based cryptography
NTRU Prime
Post-quantum cryptography
VHDL