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On enhancing the security against memory disclosure attacks

Publikationstyp
Conference Paper
Date Issued
2025-09
Sprache
English
Author(s)
Ghosh, Prokash  
Kumar, Gaurav  
Lal, Sohan  
Massively Parallel Systems E-EXK5  
Ahlawat, Satyadev  
Virendra Singh
TORE-URI
https://hdl.handle.net/11420/60238
Start Page
1
End Page
6
Citation
IEEE 38th International System-on-Chip Conference, SOCC 2025
Contribution to Conference
IEEE 38th International System-on-Chip Conference, SOCC 2025  
Publisher DOI
10.1109/socc66126.2025.11235448
Publisher
IEEE
ISBN of container
979-8-3315-9478-7
979-8-3315-9478-7
Main memory is a critical component for storing computational data across various applications, including highly sensitive information such as banking transactions, encryption keys, and authentication credentials. However, memory systems are susceptible to side-channel attacks, making it imperative to implement effective countermeasures against unauthorized data extraction. Additionally, counterfeit memory controllers and memory devices pose a significant security risk, as they can facilitate data leakage even in the presence of conventional encryption mechanisms. Traditional security solutions, such as AES encryption integrated into memory controllers, provide strong cryptographic protection; however, they introduce substantial latency and area overhead. This paper presents a novel security countermeasure that ensures secure communication between the memory controller and the memory device by employing XOR-based encryption and decryption at both ends. The proposed technique remains secure even in the presence of unauthenticated memory components, preventing unauthorized data access. Experimental evaluations demonstrate that the proposed approach achieves a high level of security (2512) while significantly reducing area overhead and incurring no additional access latency.
Subjects
Memory disclosure attacks
Cold boot attacks
DMA attacks
DRAM
LFSR
Warm boot attacks
DDC Class
004: Computer Sciences
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