AVR processors as a platform for language-based security

Publikationstyp
Conference Paper
Date Issued
2017-09
Sprache
English
Author(s)
Dewald, Florian  
Mantel, Heiko 
Weber, Alexandra  
TORE-URI
http://hdl.handle.net/11420/13858
First published in
Lecture notes in computer science  
Number in series
10492 LNCS
Start Page
427
End Page
445
Citation
Lecture Notes in Computer Science 10492 LNCS: 427-445 (2017)
Contribution to Conference
22nd European Symposium on Research in Computer Security, ESORICS 2017  
Publisher DOI
10.1007/978-3-319-66402-6_25
Scopus ID
2-s2.0-85029543234
Publisher
Springer International Publishing AG
AVR processors are widely used in embedded devices. Hence, it is crucial for the security of such devices that cryptography on AVR processors is implemented securely. Timing-side-channel vulnerabilities and other possibilities for information leakage pose serious dangers to the security of cryptographic implementations. In this article, we propose a framework for verifying that AVR assembly programs are free from such vulnerabilities. In the construction of our framework, we exploit specifics of the 8-bit AVR architecture to make the static analysis of timing behavior reliable. We prove the soundness of our analysis against a formalization of the official AVR instruction-set specification.
DDC Class
004: Informatik