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Optimal DC/AC data bus inversion coding
Publikationstyp
Conference Paper
Date Issued
2018-03
Sprache
English
Author(s)
Volume
2018-January
Start Page
1063
End Page
1068
Citation
Design, Automation and Test in Europe Conference and Exhibition (DATE 2018)
Contribution to Conference
Publisher DOI
Scopus ID
ISBN of container
978-398192631-6
GDDR5 and DDR4 memories use data bus inversion (DBI) coding to reduce termination power and decrease the number of output transitions. Two main strategies exist for encoding data using DBI: DBI DC minimizes the number of outputs transmitting a zero, while DBI AC minimizes the number of signal transitions. We show that neither of these strategies is optimal and reduction of interface power of up to 6% can be achieved by taking both the number of zeros and the number of signal transitions into account when encoding the data. We then demonstrate that a hardware implementation of optimal DBI coding is feasible, results in a reduction of system power and requires only an insignificant additional die area.
Subjects
Data bus inversion
DDR4
GDDR5
power consumption
termination power