A 10-b 5-GS/s passive T/H assisted time-interleaved pipelined-SAR ADC with pre-quantization and background offset calibration

This letter presents a 10-bit 5-GS/s time-interleaved (TI) pipelined successive-approximation-register (SAR) analogue-to-digital converter (ADC). By utilizing a full-speed passive track-and-hold circuit (T/H), pre-quantization can be performed in parallel, alleviating the timing constraint in the first stage. The chopped switches in the passive T/H enable input-independent background offset calibration for comparators and residue amplifiers. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 51.8-dB SNDR and 67.9-dB SFDR at the Nyquist input.

Subjects

analogue circuits

analogue-digital conversion

calibration

DDC Class

621.38: Electronics, Communications Engineering

Lizenz

https://creativecommons.org/licenses/by-nc-nd/4.0/

Publication version

publishedVersion

Name

Electronics Letters - 2026 - Yu - A 10‐b 5‐GS s Passive T H Assisted Time‐Interleaved Pipelined‐SAR ADC With.pdf

Type

Main Article

Size

1.75 MB

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Adobe PDF

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A 10-b 5-GS/s passive T/H assisted time-interleaved pipelined-SAR ADC with pre-quantization and background offset calibration