WCET Analysis of shared caches in multi-core architectures using event-arrival curves

Volume
2023-April
Start Page
1
End Page
2
Citation
Design, Automation and Test in Europe (DATE 2023)
Contribution to Conference
Design, Automation, and Test in Europe Conference and Exhibition, DATE 2023  
Publisher DOI
10.23919/DATE56975.2023.10137034
Scopus ID
2-s2.0-85162656999
Publisher
Institute of Electrical and Electronics Engineers Inc.
ISBN
978-398192637-8
We propose a novel analysis approach for shared LRU caches to classify accesses as definitive cache hits or potential misses. In this approach inter-core cache interference is modelled as an event stream. Thus, by analyzing the timing between subsequent accesses to a particular cache block, it is possible to bound the inter-core interference. This perspective allows us to classify accesses as cache hits or potential misses using a data-flow analysis. We compare the performance of the presented approach to a partitioning of the shared cache.
Subjects
multi-core
shared cache
WCET analysis
DDC Class
600: Technology