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Bus-aware static instruction SPM allocation for multicore hard real-time systems
Citation Link: https://doi.org/10.15480/882.2588
Publikationstyp
Conference Paper
Date Issued
2017-06-01
Sprache
English
Author(s)
Institut
TORE-DOI
TORE-URI
First published in
Number in series
76
Start Page
1
End Page
22
Citation
Leibniz International Proceedings in Informatics, LIPIcs (76): 1-22 (2017-06-01)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
Schloss Dagstuhl - Leibniz-Zentrum für Informatik GmbH, Dagstuhl Publishing
Over the past years, multicore systems emerged into the domain of hard real-time systems. These systems introduce common buses and shared memories which heavily influence the timing behavior. We show that existing WCET optimizations may lead to suboptimal results when applied to multicore setups. Additionally we provide both a genetic and a precise Integer Linear Programming (ILP)-based static instruction scratchpad memory allocation optimization which are capable of exploiting multicore properties, resulting in a WCET reduction of 26% in average compared with a bus-unaware optimization. Furthermore, we show that our ILP-based optimization's average runtime is distinctively lower in comparison to the genetic approach. Although limiting the number of tasks per core to one and partially exploiting private instruction SPMs, we cover the most crucial elements of a multicore setup: the interconnection and shared resources.
Subjects
Compiler
Multicore
Optimization
Real-time
WCET
DDC Class
004: Informatik
More Funding Information
Deutsche Forschungsgemeinschaft (DFG)
This work was partially supported by COST Action IC1202: Timing Analysis On Code-Level (TACLe).
This work was partially supported by COST Action IC1202: Timing Analysis On Code-Level (TACLe).
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