3.35V High Voltage Electroforming System in 28nm with 5.3mV ripple and 46 % efficiency for HfO2-based Memristors

This work demonstrates an on-chip high voltage (HV) generation, which is a critical requirement for memristor electroforming (EF) but is typically absent in smaller technology nodes. Key achievements of this study includes: (1) the development of a three-stage charge pump (CP) with an efficiency of 46.5%, delivering an EF voltage VEF of 3.35V with a compliance current Icc of 184.9μA from a 1.8V supply voltage Vdd, without the need for HV-transistors in 28nm CMOS process, and is based on preliminary work presented at the 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) in Volos, Greece (Shamookh et al., 2024); (2) the electrostatic discharge (ESD) protection, meeting the requirements of Class C3 CDM (±300V) and Class 1C HBM (±1.5kV) as per JEDEC standards (Semenov et al., 2008), employing three ESD diodes to handle positive (>3.3V) triggering ESD events and a single ESD diode for negative triggering ESD events above −1.87V; and (3) the on-chip EF architecture for a 64 × 64 memristor crossbar array, as an active matrix (AM), through source and gate control of the compliance transistor. A ripple detection stage monitors voltage ripple at the three-stage CP bit-line (BL), halting gate pulses to the active compliance transistor and triggering EF for the next memristor in the left-to-right sequence. The proposed design is scalable to any m×n array and adaptable to various memristor applications, paving the way for fully integrated EF solutions in advanced technology nodes.

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621.3: Electrical Engineering, Electronic Engineering

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https://creativecommons.org/licenses/by/4.0/

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1-s2.0-S1434841125002043-main.pdf

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3.35V High Voltage Electroforming System in 28nm with 5.3mV ripple and 46 % efficiency for HfO2-based Memristors