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A 500 MS/s Robust 2b/cycle Pipelined-SAR ADC Achieving 64.6-dB SNDR and 82.6-dB SFDR With Linearity Enhancement Techniques
Publikationstyp
Journal Article
Date Issued
2026
Sprache
English
Author(s)
Zhu, Zheng
Zhang, Lulu
Huang, Qin
Feng, Yao
Liang, Chao
Hu, Biao
Du, Ling
Yang, Rongbin
Wu, Shuangyi
Volume
9
Start Page
9
End Page
12
Citation
IEEE Solid State Circuits Letters 9: 9-12 (2026)
Publisher DOI
Scopus ID
Publisher
IEEE
This letter presents a 14-bit 500-MS/s 3-stage pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). By exploiting robust 2b/cycle SAR ADCs, this ADC incorporates significant voltage and time redundancy. High SFDR is achieved through several linearity enhancement techniques. First, a DAC splitting technique addresses the common-mode voltage matching problem between the input buffer and the sampling circuit. Second, a reference charge neutralization minimizes reference ripple. Finally, a digital harmonic correction is realized with a low-cost and low-latency LUT. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 64.6-dB SNDR and 82.6-dB SFDR at Nyquist.
Subjects
2b/cycle
analog-to-digital converter (ADC)
linearity enhancement techniques
pipelined-successive-approximation-register (SAR) ADC
DDC Class
600: Technology
621.3: Electrical Engineering, Electronic Engineering