FPGA implementations of radix-10 digit recurrence fixed-point and floating-point dividers

Publikationstyp
Conference Paper
Date Issued
2011
Sprache
English
Author(s)
Baesler, Malte  
Voigt, Sven-Ole  
Teufel, Thomas  
Institut
Zuverlässiges Rechnen E-19  
TORE-URI
http://hdl.handle.net/11420/7921
Start Page
13
End Page
19
Article Number
6128548
Citation
International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011: 6128548, 13-19 (2011)
Contribution to Conference
International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011  
Publisher DOI
10.1109/ReConFig.2011.41
Scopus ID
2-s2.0-84856857903
Publisher
IEEE
In this paper we present three different radix-10 digit recurrence division algorithms for FPGA architectures. The first one implements the simple shift-and-subtract algorithm, whereas the second and third implementations each perform digit recurrence algorithm with signed-digit redundant quotient alculation and carry-save representation of the residuals. However, the second divider computes the quotient digit using a ROM whereas the third divider uses a quotient digit decomposition and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA and implementation results are given.
Subjects
decimal
digit recurrence
division
floating-point
FPGA
IEEE 754-2008
radix-10
DDC Class
004: Informatik
510: Mathematik