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Impact of parasitic elements on the performance of digital CMOS circuits with Gigabit feature size
Publikationstyp
Conference Paper
Date Issued
2003-07
Sprache
English
Journal
Volume
47
Issue
7 SPEC.
Start Page
1243
End Page
1248
Citation
Solid-State Electronics 47 (7): 1243-1248 (2003)
Publisher DOI
Scopus ID
Publisher
Elsevier
This paper discusses the impact of the interconnect parameters on the signal delay of digital CMOS circuits. The minimum feature size for simulated MOSFETs was scaled in the range from 100 to 10 nm and interconnects were scaled down to 25 nm feature size. Our results show that new parasitic effects, as the size effect for copper and the increase of the threshold voltage due to direct tunneling gate current, will partly compensate the performance gain obtained by using new materials. These effects must be considered for minimum feature sizes below 50 nm. The influences have been studied on a logical unit and on on-chip interconnect scheme.
Subjects
Gate current
Interconnects
Parasitics
Size effect
DDC Class
621.3: Electrical Engineering, Electronic Engineering