Integrated circuit with memristor emulator array and neuron circuits for neuromorphic pattern recognition
Publikationstyp
Conference Paper
Date Issued
2016
Sprache
English
Author(s)
Start Page
265
End Page
268
Article Number
7760875
Citation
International Conference on Telecommunications and Signal Processing, TSP: 7760875 (2016-11-28)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE
ISBN
978-1-5090-1288-6
978-1-5090-1289-3
978-1-5090-1287-9
This paper details an array of switch resistor based memristor emulators with integrate & fire based neuron ASIC for the development of memristor based pattern recognition. The designed ASIC has 4 memristor emulators with a conductance range from 195 nS to 190 uS; processing has been planned to be off-chip to get the freedom of programmability of any function in ASIC. The ASIC has 2 integrate and fire (I & F) neuron circuits which are planned to be used in conjunction with memristors in a large multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neurons and an algorithm of pattern recognition simulated in Ltspice. The ASIC has been fabricated in AMS 350nm process.
Subjects
ASIC
Emulator
Memristor
Neuron
Pattern recognition
DDC Class
621.3: Electrical Engineering, Electronic Engineering