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Design space exploration for printed circuit board vias using polynomial chaos expansion
Publikationstyp
Conference Paper
Date Issued
2016-09-19
Sprache
English
Author(s)
Institut
TORE-URI
First published in
Number in series
2016 September
Start Page
812
End Page
817
Article Number
7571754
Citation
IEEE International Symposium on Electromagnetic Compatibility (EMC 2016): 7571754, 812-817
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE
ISBN
978-1-5090-1442-2
978-1-5090-1441-5
978-1-5090-1439-2
978-1-5090-1443-9
This work discusses how the Williamson equivalent circuit for the modeling of via transitions is augmented using the polynomial chaos expansion (PCE) method to take into account stochastic variations of model parameters. In addition, it is shown how the PCE can be applied in combination with Monte-Carlo (MC) sampling to conduct an efficient design space analysis. The physics-based via (PBV) model is used to efficiently model multilayer via interconnects by concatenating equivalent circuit models representing certain geometric sections of the interconnect. These equivalent circuits are expanded with respect to the stochastic model parameters by means of PCE and concatenated to derive an augmented model of the whole interconnect. From this representation, stochastic scattering parameters are extracted. Numerical examples verify the method and the computational advantages over MC sampling. The method provides a fast and comprehensive approach to design space exploration and variability assessment in the design stage of via interconnects. The presented approach is not limited to via models and can be applied to various microwave structures in a similar way.
Subjects
design space exploration
high-speed digital interconnects
physics-based via (PBV) model
polynomial chaos expansion (PCE)
printed circuit board (PCB)
DDC Class
600: Technik