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Compiling for the worst case : memory allocation for multi-task and multi-core hard real-time systems
Citation Link: https://doi.org/10.15480/882.2713
Publikationstyp
Journal Article
Date Issued
2020-03
Sprache
English
Author(s)
Institut
TORE-DOI
TORE-URI
Volume
19
Issue
2
Start Page
1
End Page
26
Article Number
14
Citation
ACM Transactions on Embedded Computing Systems 2 (19): 14, 1-26 (2020)
Publisher DOI
Scopus ID
Publisher
ACM Press
Modern embedded hard real-time systems feature multiple tasks running on multiple processing cores. Schedulability analysis of such systems is usually performed on an abstract system level with each task being represented as a black box with fixed timing properties. If timing constraints are violated, optimizing the system on a code-level in order to achieve schedulability is a tedious task.
To tackle this issue, we propose an extension to the WCET-Aware C Compiler framework WCC. We integrated an optimization framework based on Integer-Linear Programming into the WCC which is able to optimize a multi-core system with multiple tasks running on each core with regards to its schedulability. We evaluate the framework by providing two approaches on a schedulability aware static Scratchpad Memory (SPM) allocation: One based on Integer-Linear Programming (ILP) and one based on a genetic algorithm.
To tackle this issue, we propose an extension to the WCET-Aware C Compiler framework WCC. We integrated an optimization framework based on Integer-Linear Programming into the WCC which is able to optimize a multi-core system with multiple tasks running on each core with regards to its schedulability. We evaluate the framework by providing two approaches on a schedulability aware static Scratchpad Memory (SPM) allocation: One based on Integer-Linear Programming (ILP) and one based on a genetic algorithm.
Subjects
WCET optimization
multi-core systems
scheduling analysis
DDC Class
004: Informatik
More Funding Information
Deutsche Forschungsgemeinschaft (DFG)
Publication version
publishedVersion
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