An 8-Bit precision 10T SRAM compute-in-memory macro using ADC with small area

This brief proposes a charge-domain analog Compute-In-Memory (CIM) architecture based on multi-bit SRAM. The proposed structure consists of a 64×64 10T1C SRAM array, which can perform 1024 MAC operations between 4-bit signed input and weight within a single clock cycle. An 8-bit Analog-to-Digital Converter (ADC) is employed for quantization, converting the analog Multiply-Accumulate (MAC) results into 8-bit digital signals for output. The ADC module adopts capacitor array multiplexing, pseudo-differential sampling with double-terminal flipping method and matching layout designing to save area. The proposed circuit is implemented in 28nm process which operates at a supply voltage of 0.8V. It achieves an energy efficiency of 184 TOPS/W and an area efficiency of 7.3 TOPS/mm², and reaches an accuracy of 86.9% in the training on CIFAR-10 dataset. When compared with other works, the highlight of this work is the highest energy efficiency and the highest area efficiency on 4-bit input and weight precision normalized to 28nm.

Subjects

Charge-Domain

Compute-In-Memory (CIM)

Deep Neural Networks (DNNs)

SRAM

Successive Approximation Register (SAR) ADC

DDC Class

600: Technology

621.3: Electrical Engineering, Electronic Engineering

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An 8-Bit precision 10T SRAM compute-in-memory macro using ADC with small area