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  4. SeismicSense: phase picking of seismic events with embedded machine learning
 
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SeismicSense: phase picking of seismic events with embedded machine learning

Publikationstyp
Conference Paper
Date Issued
2025-03
Sprache
English
Author(s)
Zainab, Tayyaba  
Harms, Laura 
Karstens, Jens  
Landsiedel, Olaf  
TORE-URI
https://hdl.handle.net/11420/59581
Start Page
551
End Page
559
Citation
40th Annual ACM Symposium on Applied Computing, SAC 2025
Contribution to Conference
40th Annual ACM Symposium on Applied Computing, SAC 2025  
Publisher DOI
10.1145/3672608.3707845
Publisher
ACM
ISBN of container
979-8-4007-0629-5
Analyzing seismic data is essential for understanding natural geological processes and anthropogenic activities, particularly in localizing seismic events. While recent advances in seismic analysis rely heavily on resource-intensive machine learning approaches, these methods are impractical in resource-constrained environments such as underwater, underground, or rural areas. To address this, we introduce SeismicSense, a lightweight neural network (NN)-based solution for sensor-level seismic data analysis. SeismicSense detects seismic events and localizes them by identifying seismic event phases through a cascading architecture. Initially, SeismicSense uses an NN to filter out non-earthquake events, minimizing false positives. Upon identifying an earthquake, it detects the P- and S- phases, which are crucial for determining the origin and magnitude of seismic activity. SeismicSense significantly reduces data transmission by communicating only the arrival times of these phases to the cloud, enabling efficient and selective communication during seismic events. Despite being 20 times smaller than state-of-the-art models and requiring just 186 KB of RAM, SeismicSense achieves exceptional performance, with F1-scores of 99.4% for earthquake detection, 98% for P-wave detection, and 96% for S-wave detection. Additionally, leveraging integer acceleration on modern MCUs enhances efficiency, reducing inference time on Cortex-M MCUs by 18-fold compared to non-accelerated methods, enabling real-time execution.
DDC Class
004: Computer Sciences
Funding(s)
HIDSS-
TUHH
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