FPGA implementation of a decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier

Publikationstyp
Conference Paper
Date Issued
2009-12-01
Sprache
English
Author(s)
Baesler, Malte  
Teufel, Thomas  
Institut
Zuverlässiges Rechnen E-19  
TORE-URI
http://hdl.handle.net/11420/8563
Start Page
6
End Page
11
Article Number
5382019
Citation
ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs: 5382019, 6-11 (2009-12-01)
Contribution to Conference
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2009  
Publisher DOI
10.1109/ReConFig.2009.17
Scopus ID
2-s2.0-77950482315
Publisher
IEEE
ISBN of container
978-1-4244-5293-4
978-0-7695-3917-1
Decimal Floating Point (DFP) operations are very important for applications, that cannot tolerate errors from conversions between binary and decimal formats, for instance scientific, commercial, financial and internet-based applications. In this paper we present a parallel decimal fixed-point multiplier, designed to exploit the features of FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation and a BCD-4221 Carry Save Adder reduction tree [1]. Furthermore, we extend the multiplier with an accurate scalar product unit in order to provide an important operation with smallest possible rounding error as proposed in [2]. Finally the design is implemented and tested on a Xilinx Virtex-II Pro FPGA platform.
Subjects
Accurate scalar product
Decimal multiplier
Floating point
FPGA
IEEE 754-2008
DDC Class
004: Informatik
510: Mathematik