Circuit design methodology of radiation-tolerant DAC for space applications

Publikationstyp
Conference Paper
Date Issued
2024
Sprache
English
Author(s)
Suresh, Aishwarya Harneer  
IHP-Leibniz-Institut für Innovative Mikroelektronik
Singer, Julian Alexander  
Integrierte Schaltungen E-9  
Fischer, Gunter  
IHP-Leibniz-Institut für Innovative Mikroelektronik
TORE-URI
https://hdl.handle.net/11420/47480
Citation
7th Panhellenic Conference on Electronics and Telecommunications (PACET 2024)
Contribution to Conference
7th Panhellenic Conference on Electronics and Telecommunications, PACET 2024  
Publisher DOI
10.1109/PACET60398.2024.10497042
Scopus ID
2-s2.0-85191660305
Publisher
IEEE
ISBN
9798350318845
In this paper, a general circuit design methodology for space applications is presented with an 8-bit resistive DAC with XY addressing mode and BiCMOS buffer designed in SiGe BiCMOS technology. Circuit-level simulations are performed to evaluate the radiation tolerance of the DAC. Simulations show that even though the DAC core circuit is immune to radiation effects, auxiliary circuits are highly susceptible to analog single-event transients (ASETs). Circuit-level mitigation techniques are addressed, resulting in a DAC that is estimated to be immune to 60 MeVcm2/mg SET. The total current consumption with 3.3 V supply is 0.58 mA at 1 MHz sampling frequency.
Subjects
ASET
DAC
radiation tolerant
SiGe BiCMOS technology
Space applications
TID
DDC Class
0: Computer Science, Information and General Works::005: Computer Programming, Programs, Data and Security::005.1: Programming