Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array

In this paper, we present the architecture of a coarse-grain reconfigurable cell designed for pipelined arithmetic computing applications. We apply the concept of separation between control-path and computation-path logic in the so-called reconfigurable coprocessor array architecture. Variations of the cells are implemented on CMOS 0.35 and 0.13 technologies and subjected to a group of benchmarks. The resulting delay area products showed that dual-ALU cells have about 50% smaller area-delay product than the single-ALU cell has.

Subjects

Coarse-grain

Coprocessor

Distributed arithmetic

Pipeline

Reconfigurable

DDC Class

621.3: Electrical Engineering, Electronic Engineering

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Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array