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  4. Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array
 
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Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array

Publikationstyp
Conference Paper
Date Issued
2007
Sprache
English
Author(s)
Hanoun, Abdulrahman
Eingebettete Systeme E-13  
Manteuffel, Henning  
Eingebettete Systeme E-13  
Mayer-Lindenberg, Fritz  
Eingebettete Systeme E-13  
Galjan, Wjatscheslaw  
Eingebettete Systeme E-13  
TORE-URI
https://hdl.handle.net/11420/49268
Start Page
832
End Page
835
Article Number
4728448
Citation
IEEE International Conference on Signal Processing and Communications (ICSPC 2007)
Contribution to Conference
1st IEEE International Conference of Signal Processing and Communications, ICSPC 2007  
Publisher DOI
10.1109/ICSPC.2007.4728448
Scopus ID
2-s2.0-60249103963
Publisher
IEEE
ISBN
1-4244-1236-6
978-1-4244-1236-5
In this paper, we present the architecture of a coarse-grain reconfigurable cell designed for pipelined arithmetic computing applications. We apply the concept of separation between control-path and computation-path logic in the so-called reconfigurable coprocessor array architecture. Variations of the cells are implemented on CMOS 0.35 and 0.13 technologies and subjected to a group of benchmarks. The resulting delay area products showed that dual-ALU cells have about 50% smaller area-delay product than the single-ALU cell has.
Subjects
Coarse-grain
Coprocessor
Distributed arithmetic
Pipeline
Reconfigurable
DDC Class
621.3: Electrical Engineering, Electronic Engineering
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