RiCaSi: Rigorous cache side channel mitigation via selective circuit compilation

Publikationstyp
Conference Paper
Date Issued
2020-12-09
Sprache
English
Author(s)
Mantel, Heiko 
Scheidel, Lukas  
Schneider, Thomas  
Weber, Alexandra  
Weinert, Christian  
Weißmantel, Tim  
TORE-URI
http://hdl.handle.net/11420/13819
First published in
Lecture notes in computer science  
Number in series
12579 LNCS
Start Page
505
End Page
525
Citation
Lecture Notes in Computer Science 12579 LNCS: 505-525 (2020)
Contribution to Conference
19th International Conference on Cryptology and Network Security, CANS 2020  
Publisher DOI
10.1007/978-3-030-65411-5_25
Scopus ID
2-s2.0-85098280110
Publisher
Springer
Cache side channels constitute a persistent threat to crypto implementations. In particular, block ciphers are prone to attacks when implemented with a simple lookup-table approach. Implementing crypto as software evaluations of circuits avoids this threat but is very costly. We propose an approach that combines program analysis and circuit compilation to support the selective hardening of regular C implementations against cache side channels. We implement this approach in our toolchain RiCaSi. RiCaSi avoids unnecessary complexity and overhead if it can derive sufficiently strong security guarantees for the original implementation. If necessary, RiCaSi produces a circuit-based, hardened implementation. For this, it leverages established circuit-compilation technology from the area of secure computation. A final program analysis step ensures that the hardening is, indeed, effective.
DDC Class
004: Informatik