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Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning
Publikationstyp
Journal Article
Date Issued
2014-02-22
Sprache
English
Author(s)
Institut
TORE-URI
Journal
Volume
38
Issue
8
Start Page
845
End Page
859
Citation
Microprocessors and Microsystems 8 (38): 845-859 (2014)
Publisher DOI
Scopus ID
Publisher
Elsevier
There is a trend towards to dense integration of embedded systems for cost, weight, and power savings. Integration of multiple critical software functions in a single embedded platform requires domain partitioning. Groups of independent software functions exist in isolated domains to maintain individual functional correctness, even in presence of errors. Software solutions such as Real-Time Operating Systems (RTOS) with time and space partitioning are state-of-the-art segregation approaches. As an alternative to these existing solutions, we present a robust, reliable, and efficient architecture with segregation support for safety- and security-critical embedded systems. Our solution hosts different software functions on a platform with as few hardware components as possible: the System-on-a-Chip (SoC) approach. The proposed architecture instantiates multiple self-contained soft processor systems on a single chip. The architecture offers hardware-enforced segregation and is completely transparent to software applications. We demonstrate this aspect by running multiple segregated instances of unmodified off-the-shelf Linux systems from a shared memory device. Since our architecture targets reconfigurable platforms, it is also flexible and can be tailored to application-specific needs at design time. Segregation is achieved with a hierarchical connection of memory busses by secure bus bridges. The bridges perform caching, prefetching, and burst accesses to efficiently avoid temporal conflicts on shared resources. Hence, our secure bridges allow to use soft processors for critical designs. We implement several prototypes and evaluate them by using novel bus observers for characterization of bus-centric architectures. Finally, we show the effectiveness of our implemented optimizations.
Subjects
Bus-centric architecture
Domain partitioning
FPGA
MPSoC
Performance evaluation
Shared memory
DDC Class
004: Informatik
510: Mathematik