FPGA-specific optimizations by partial function evaluation

Publikationstyp
Conference Paper
Date Issued
2011
Sprache
English
Author(s)
Manteuffel, Henning  
Başsoy, Cem Savaş  
Mayer-Lindenberg, Georg Friedrich 
Institut
Eingebettete Systeme E-13  
TORE-URI
http://hdl.handle.net/11420/13503
Start Page
1
End Page
6
Article Number
5952283
Citation
2011 Electronic System Level Synthesis Conference, ESLsyn 2011 (): 5952283 1-6 (2011)
Contribution to Conference
2011 Electronic System Level Synthesis Conference, ESLsyn 2011  
Publisher DOI
10.1109/ESLsyn.2011.5952283
Scopus ID
2-s2.0-80052008768
Publisher
IEEE
Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%. © 2011 IEEE.
Subjects
FPGA
High-level synthesis
optimizations
partial evaluation
DDC Class
600: Technik
620: Ingenieurwissenschaften