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Real-time adaptive signal processing using a dynamic reconfigurable systolic architecture in analog VLSI
Publikationstyp
Conference Paper
Date Issued
1999-05
Sprache
English
Author(s)
Institut
Volume
3
Start Page
58
End Page
61
Citation
IEEE International Symposium on Circuits and Systems, (ISCAS 1999)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE
ISBN of container
978-0-7803-5473-9
978-0-7803-5471-5
978-0-7803-5472-2
Reconstruction of given noisy data is an ill-posed problem and a computationally intensive task. Non-linear regularisation techniques are used to find a unique solution under certain constraints. In our contribution we present a parallel mixed-signal architecture which solves this non-linear problem within microseconds. By connecting all parallel cells in a circular manner it is possible to process noisy data vectors of infinite length. This is achieved by virtually shifting the non-linear adaptive filter kernel over the noisy data vector. A 1-D experimental chip has been fabricated using 0.8μm CMOS technology. On-chip measurements are shown to agree with results from numerical simulations. Results from applying the 1-D chip to non linear smoothing of image data will also be given correspondence.
DDC Class
600: Technik
620: Ingenieurwissenschaften