Retention tail improvement for Gbit DRAMs through trap passivation confirmed by activation energy analysis

Start Page
250
End Page
253
Article Number
4099903
Citation
Proceedings of the 36th European Solid-State Device Research Conference, 2006, ESSDERC 2006, 19 - 21 Sept. 2006, Montreux, Switzerland. - Seite 250-253
Contribution to Conference
36th European Solid-State Device Research Conference, ESSDERC 2006  
Publisher DOI
10.1109/essder.2006.307685
Scopus ID
2-s2.0-78650870403
Publisher
IEEE
ISBN
1-4244-0301-4
978-1-4244-0301-1
A very efficient method to reduce gate induced drain leakage (GIDL) as the dominant leakage path in the tail part of DRAM data retention time distribution is presented. Different to other reports, GIDL is addressed by trap passivation instead of lowering of electric fields. Stable passivation of traps is achieved by implantation of fluorine into S/D regions of 512Mbit and 1Gbit DRAMs in 110 nm technology. It was found that the position of the F-implant within the process flow plays a key role to enable trap reduction and retention tail improvement. Systematic implant experiments were carried out resulting in a failcount reduction of up to 40 %. Detailed activation energy analysis on individual memory cells confirms the validity of the retention tail model and the selective reduction of GIDL traps by fluorine implantation.
Subjects
Activation energy
DRAM
Fluorine
Retention
DDC Class
621.3: Electrical Engineering, Electronic Engineering