Options
The influence of fluorine on various mos devices
Publikationstyp
Conference Paper
Date Issued
1999
Sprache
English
Author(s)
Innertsberger, G.
Jurk, R.
Felsner, J.
Kakoschke, R.
Yuwono, B.
Schlösser, T.
Gschwandtner, A.
Volume
567
Start Page
589
End Page
595
Citation
In: Proceedings of the Materials Research Society Symposium 1999 : 589-595 (1999)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
Materials Reserach Society
The influence of Vapor Phase Precleans leads to a different controllable fluorine content within the subsequently grown dielectric. The influence of the clean is discussed for non-volatile memory devices, advanced MOS transistors and ultra thin gate dielectrics. On the one hand, the QM values for in situ cleaned samples are lower than for wet cleaned samples. Performing cycle stress on the EEPROM devices, the tunnel oxide (7.5nm) degrades the quicker with the increase in fluorine concentration within the oxide. On the other hand, MOS transistor characteristics show a significant improvement on the negative bias temperature instability (NBTI) in the PMOS threshold voltage. MOS transistors with ultra thin gate dielectrics (1.5nm) show the expected significant increase of the saturation current compared with 0.35μm technology (tox=7.5nm). Excellent times until soft breakdown for ultra thin dielectrics are found when the in situ cleaning is used. ©1999 Materials Research Society.
DDC Class
621.3: Electrical Engineering, Electronic Engineering