DuRTL - information flow analysis tool for register transfer level hardware designs

In this tool paper, we present a design information flow analysis tool called DuRTL. DuRTL is an open-source hardware information flow analysis tool implemented in C++ that helps designers understand and comprehend unknown hardware designs written in Verilog and VHDL. DuRTL implements an approach for Hardware Information Flow Tracking based on a tagging mechanism where unique tags are injected into a hardware design. Each tag is associated with a signal at a specific time and identifies a flow of information during the traversal of the circuit. We explain the methodology and IFT implementation of DuRTL and some of the design choices made during the development. We also present some experiments that show the capabilities of DuRTL.

Subjects

Hardware | Information Flow Tracking | Verilog

DDC Class

600: Technology

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DuRTL - information flow analysis tool for register transfer level hardware designs