Radiation-tolerant all-digital PLL/CDR with varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5MeVcm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40MHz to 320MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11mW and an FOM of −235 dB.

Subjects

All-Digital

PLL

CDR

Single-Event Effects

radiation hardening

DDC Class

600: Technik

620: Ingenieurwissenschaften

Funding Organisations

Bundesministerium für Bildung und Forschung (BMBF)

More Funding Information

This work was funded by the Wolfgang Gentner Programme of the German Federal Ministry of Education and Research (grant no. 05E18CHA).

Publication version

publishedVersion

Lizenz

https://creativecommons.org/licenses/by/4.0/

Name

electronics-10-02741.pdf

Size

3.58 MB

Format

Adobe PDF

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Radiation-tolerant all-digital PLL/CDR with varactorless LC DCO in 65 nm CMOS