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Array test structure for ultra-thin gate oxide degradation issues
Publikationstyp
Conference Paper
Date Issued
2009
Sprache
English
Start Page
85
End Page
90
Article Number
4814616
Citation
2009 IEEE International Conference on Microelectronic Test Structures, ICMTS, Oxnard, CA, USA, 2009, pp. 85-90
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE
ISBN
9781424442591
An array test structure for highly parallelized measurements of ultra-thin MOS gate oxide failures caused by degradation is presented. The test structure allows for voltage stress tests of several thousand NMOS devices under test (DUTs) in parallel to provide a large and significant statistical base regarding soft as well as hard breakdown and stress induced degradation of transistor parameters. The array has been fabricated in a standard 130 nm CMOS technology. As mixed mode technologies provide both thin and thick oxide MOS transistors, different gate oxide thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages.
DDC Class
621.3: Electrical Engineering, Electronic Engineering