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A multi-core FPGA-based SoC architecture with domain segregation
Publikationstyp
Conference Paper
Date Issued
2012-12
Sprache
English
Author(s)
Institut
TORE-URI
Start Page
1
End Page
7
Article Number
6416764
Citation
International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012: 6416764, 1-7 (2012-12)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE
Nowadays, FPGAs are sufficiently large to host not only single soft-core CPUs but a whole Multi-Processor System-on-a-Chip (MPSoC). They follow the recent trend of chip-multiprocessing. Given the requirement for domain segregation in safety and security related applications, we propose an FPGA-based architecture that achieves segregation by secure bus bridges. According to the SoC-paradigm, we use a single shared memory controller to reduce external component count. We pay special attention to performance evaluation and avoidance of temporal conflicts. The architecture is evaluated by dedicated bus observers using simulation and hardware prototypes and is finally benchmarked by running multiple isolated off-the-shelf Linux systems. © 2012 IEEE.
Subjects
domain segregation
FPGA
isolation
MPSoC
partitioning
shared memory
DDC Class
004: Informatik
510: Mathematik