A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a Virtex-5 FPGA

Decimal Floating Point operations are important for applications that cannot tolerate errors from conversionsbetween binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, wepresent a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is basedon BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipelinestages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unitfor IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unitand migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accuratescalar product unit's latency even by a factor of five.

Subjects

decimal floating point operation

DDC Class

620: Ingenieurwissenschaften

Lizenz

https://creativecommons.org/licenses/by/3.0/

Name

IJRC.2010.357839.pdf

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887.93 KB

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Adobe PDF

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A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a Virtex-5 FPGA