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Secure and efficient hardware implementations of NTRU Prime
Citation Link: https://doi.org/10.15480/882.15172
Publikationstyp
Doctoral Thesis
Date Issued
2025
Sprache
English
Author(s)
Advisor
Referee
Title Granting Institution
Technische Universität Hamburg
Place of Title Granting Institution
Hamburg
Examination Date
2024-11-12
TORE-DOI
Citation
Technische Universität Hamburg: (2025)
Streamlined NTRU Prime is a cryptoscheme designed to minimize the risk of deploying a lattice-based KEM, while only incurring a low performance penalty. We investigate if this performance penalty also applies to hardware implementations and whether we can reduce any penalty with specialized hardware designs. For this, we present multiple full hardware implementations of Streamlined NTRU Prime, including high-speed, low-area and side-channel protected designs. Our results show that the design goals of Streamlined NTRU Prime are not a barrier to highly efficient hardware implementations, and that many design choices are in fact conducive to competitive implementations.
Subjects
Post-Quantum Cryptography
Hardware Implementation
Lattice Cryptography
NTRU Prime
FPGA
Masking
DDC Class
005: Computer Programming, Programs, Data and Security
004: Computer Sciences
621.3: Electrical Engineering, Electronic Engineering
Funding Organisations
More Funding Information
This work was labelled by the EUREKA cluster PENTA and funded by German authorities under grant agreement PENTA-2018e-17004-SunRISE. This work was also supported by the Federal Ministryof Education and Research (BMBF) of the Federal Republic of Germany (grants 16KIS1572K, SASVI and 16KIS0658K, SysKit-HW) and by the European Commission under the grant agreement number 101070374 (CONVOLVE).
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Marotzke_Adrian_Secure-and-Efficient-Hardware-Implementations-of-NTRU-Prime.pdf
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