An area-efficient 130 nm CMOS baseband processing unit for 24 GHz FMCW radar positioning

Article Number
6374292
Citation
International Symposium on Signals, Systems and Electronics: 6374292 (2012-10)
Contribution to Conference
International Symposium on Signals, Systems and Electronics 2012  
Publisher DOI
10.1109/ISSSE.2012.6374292
This paper presents an area-efficient digital implementation of a baseband processing unit (BPU) for autonomous wireless sensor nodes with localization functionality. The presented wireless nodes should achieve a high miniaturization degree and use an onboard FMCW secondary radar for distance measurements. The challenge for designing the digital system was to reduce memory requirements towards a low cost hardware design in general, and for an ASIC design in particular. Reducing chip area implies lower energy consumption and helps saving implementation and production costs. At the same time a qualitative performance of the digital signal processing tasks while keeping the system constraints has to be assured. The introduced novel hardware implementation concept fulfill these criteria, and has been implemented and verified on a FPGA before starting the chip design. For the use case of a two-sweep-measurement-system the design has been realized as an ASIC using IBM 130nm CMOS technology.