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Dynamically reconfigurable dataflow architecture for high-performance digital signal processing
Publikationstyp
Journal Article
Date Issued
2010-08-05
Sprache
English
Author(s)
Institut
TORE-URI
Journal
Volume
56
Issue
11
Start Page
561
End Page
576
Citation
Journal of Systems Architecture 11 (56): 561-576 (2010-11-01)
Publisher DOI
Scopus ID
Publisher
Elsevier
In this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.
Subjects
Dataflow architecture
Digital signal processing
Hardware reconfiguration
Multi-FPGA platform
Parallel FFT
DDC Class
004: Informatik