Characterization of TSV-induced loss and substrate noise coupling in advanced three-dimensional CMOS SOI technology

Enthalten in
IEEE transactions on components, packaging and manufacturing technology 
Volume
3
Issue
11
Start Page
1917
End Page
1925
Article Number
6650001
Citation
IEEE Transactions on Components, Packaging and Manufacturing Technology 11 (3): Art. 6650001 i.e. Seite 1917-1925 (2013)
Publisher DOI
10.1109/TCPMT.2013.2264755
Scopus ID
2-s2.0-84887740255
Publisher
IEEE
Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps (μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design. © 2013 IEEE.
Schlagworte
3-D integrated circuit (IC)
3-D integration
On-chip interconnect
Signal integrity
Substrate noise
Through-silicon-via (TSV)
DDC Class
600: Technik
620: Ingenieurwissenschaften