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Analyzing the worst-case behavior of multi-level caches in concurrent real-time systems
Citation Link: https://doi.org/10.15480/882.16335
Publikationstyp
Doctoral Thesis
Date Issued
2025
Sprache
English
Author(s)
Advisor
Referee
Title Granting Institution
Technische Universität Hamburg
Place of Title Granting Institution
Hamburg
Examination Date
2025-12-11
Institute
TORE-DOI
Citation
Technische Universität Hamburg (2025)
This thesis tackles the analysis of the worst-case timing behavior of hard real-time systems featuring multi-level cache hierarchies. First, an analysis of inter-core cache interference in multi-core systems is presented. Second, an analysis of context-switching costs for non-inclusive cache hierarchies is presented, and flaws in the previous state-of-the-art analysis are identified. The evaluations of both analyses show that, in many situations, analysis precision is significantly improved compared to the previous state-of-the-art. Finally, an optimization to improve schedulability using cache bypassing is presented.
DDC Class
004: Computer Sciences
Publisher‘s Creditline
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Dissertation_Endversion_ThiloFischer.pdf
Size
6.17 MB
Format
Adobe PDF