A Low-Power 2nd-Order ΔΣ Modulator with a Single Current-Starving FIA

This brief presents a compact single-loop discretetime (DT) modulator. The design introduces a dual-phase 2nd-order integrator with a single current-starving floating inverter amplifier (CS-FIA). The charge dissipation and operating point shift during dynamic operation are reduced, as the FIA operates in a relatively stable subthreshold region throughout the entire clock cycle. This enables improved power efficiency across a wide supply voltage range. The ΔΣ modulator is fabricated in a 180 nm CMOS process. It achieves 102.4 dB SNDR at 256 kHz sampling frequency. With a 1.4 V supply, the circuit consumes 8.23 μW, leading to a state-of-the-art Schreier FoM of 183.2 dB. Across a supply voltage range of 1.2 V to 1.6 V, the modulator continuously maintains a FoM above 182 dB.

Subjects

analog-to-digital converter

delta–sigma modulator

floating inverter amplifier

low power

multi-bit quantizer

DDC Class

621.3: Electrical Engineering, Electronic Engineering

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A Low-Power 2nd-Order ΔΣ Modulator with a Single Current-Starving FIA