Please use this identifier to cite or link to this item: https://doi.org/10.15480/882.3910
Publisher DOI: 10.3390/electronics10222741
Title: Radiation-tolerant all-digital PLL/CDR with varactorless LC DCO in 65 nm CMOS
Language: English
Authors: Biereigel, Stefan 
Kulis, Szymon 
Moreira, Paulo Rodrigues Simoes 
Kölpin, Alexander  
Leroux, Paul 
Prinzie, Jeffrey 
Keywords: All-Digital;PLL;CDR;Single-Event Effects;radiation hardening
Issue Date: 10-Nov-2021
Publisher: Multidisciplinary Digital Publishing Institute
Source: Electronics 10 (22): 2741 (2021)
Journal: Electronics 
Abstract (english): 
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5MeVcm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40MHz to 320MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11mW and an FOM of −235 dB.
URI: http://hdl.handle.net/11420/10961
DOI: 10.15480/882.3910
ISSN: 2079-9292
Other Identifiers: doi: 10.3390/electronics10222741
Institute: Hochfrequenztechnik E-3 
Document Type: Article
Funded by: Bundesministerium für Bildung und Forschung (BMBF) 
More Funding information: This work was funded by the Wolfgang Gentner Programme of the German Federal Ministry of Education and Research (grant no. 05E18CHA).
License: CC BY 4.0 (Attribution) CC BY 4.0 (Attribution)
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